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Overview

SmartDV’s USB 2.x OTG IP is a silicon-proven, fully featured Universal Serial Bus On-The-Go solution purpose-built for SoC designs requiring flexible, dual-role USB connectivity across mobile, automotive, IoT, and consumer electronics applications. Fully compliant with USB 2.0, USB OTG and Embedded Host Revision 2.0, and USB OTG EH3 Revision 1.0, it delivers a comprehensive USB OTG implementation available in USB 2.0 Embedded Host, USB 2.0 Peripheral Only, and USB 2.0 OTG configurations — supporting High Speed, Full Speed, and Low Speed operation with xHCI-compliant host mode operation at up to 480 Mbps.

Designed to address the full breadth of USB 2.x OTG integration requirements, the IP supports Session Request Protocol (SRP), Host Negotiation Protocol (HNP), and Attach Detach Protocol (ADP) for complete OTG role switching, alongside a proprietary DMA engine for high-efficiency data transfer, configurable endpoint management, 32-bit and 64-bit internal and AXI data paths, and comprehensive root hub features for Embedded Host applications. Its software-configurable speed and HNP/ADP support, optional simple slave mode for area-optimized designs, all USB Link Power Management states L1 and L2, and system power management give SoC teams a production-tested, feature-complete USB 2.x OTG implementation suited for the most demanding mobile and embedded dual-role USB designs.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its 16-bit UTMI+ Level 3 PHY interface, AXI DMA path, AHB register path, and configurable endpoint architecture enable fast integration and confident design bring-up across a wide range of process nodes and target applications.

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USB 2.x OTG
Benefits
  • Full USB 2.x OTG Functionality – Available in USB 2.0 Embedded Host, Peripheral Only, and On-The-Go configurations supporting HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) operation
  • Complete OTG Protocol Support – Session Request Protocol (SRP), Host Negotiation Protocol (HNP) polling, Attach Detach Protocol (ADP), and OTG Device Notification registers for complete dual-role USB management
  • xHCI-Compliant Host Mode – Host mode operation compliant with xHCI v1.0 with prioritized periodic endpoint scheduling, round-robin non-periodic scheduling, and complete xHCI register implementation
  • All USB Transfer Types – Interrupt, Bulk, Isochronous, and Control transfers with High Bandwidth Interrupt and Isochronous endpoint support
  • High-Performance DMA Engine – Proprietary DMA engine with AXI interface, 32/64-bit internal and external data paths, and configurable burst length for high-efficiency USB data transfer
  • Flexible Endpoint Configuration – Software-configurable endpoints for device mode, software-configurable HS/FS/LS speed selection, and optional simple slave mode for area-optimized implementations
  • Root Hub and Embedded Host Features – LPM transaction support, USB 2.0 test mode, configurable downstream ports, and multiple HS/FS hub device support for Embedded Host applications
  • Comprehensive Power Management – USB Suspend/Resume with Remote Wakeup, HS/FS Link Power Management states L1 and L2, system Sleep, Hibernate, Warm/Cold Boot, clock gating, and multi-power-well support
Compliance and Compatibility
  • Fully compliant with USB 2.0 specification Revision 2.0 and all associated ECNs
  • Fully compliant with USB OTG and Embedded Host Revision 2.0 (USB 2.0) and all associated ECNs
  • Compliant with USB OTG and Embedded Host Supplement to USB 3.0 Specification Revision 1.0 and all associated ECNs
  • Host mode compliant with xHCI Specification v1.0
  • Compatible with 16-bit UTMI+ Level 3 PHY interface
  • Configurable SoC interface supporting AXI DMA path and AHB register path
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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