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Overview

SmartDV’s USB 2.x Host IP is a silicon-proven, fully featured Universal Serial Bus host controller solution purpose-built for SoC designs requiring reliable, high-performance USB host connectivity across embedded, automotive, IoT, and consumer electronics applications. Fully compliant with USB 2.0 and USB 2.0 Enhanced Host Controller Interface (EHCI) Revision 1.0, it delivers complete host-side USB functionality supporting High Speed (480 Mbps) operation via UTMI transceivers with full backward compatibility for Full Speed and Low Speed devices through split transaction support, providing a proven, production-ready USB host controller for the most demanding embedded SoC designs.

Designed to address the full breadth of USB 2.x host integration requirements, the IP supports Interrupt, Bulk, Isochronous, and Control transfers, descriptor and data pre-fetch and pre-compute, CRC16 and CRC5 generation and checking, prioritized scheduling for periodic endpoints, separate round-robin scheduling for periodic and non-periodic endpoint pipes, and Split Transfers for FS/LS devices connected to HS Hubs in Embedded Host Mode. Its DMA interface with configurable burst length, direct AXI/AHB/APB register addressing, USB Suspend with remote wakeup, all HS USB Link Power Management states L1 and L2, and comprehensive system power management give SoC teams a production-tested, feature-complete USB 2.x host controller optimized for power-sensitive embedded applications.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its UTMI transceiver interface, configurable DMA burst length, and direct AXI/AHB/APB register access enable fast integration and confident design bring-up across a wide range of process nodes and target applications.

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USB 2.x Host
Key Features
  • Full USB 2.x Host Controller Functionality – Complete host-side USB 2.0 EHCI implementation per EHCI Rev 1.0 supporting HS (480 Mbps) operation via UTMI transceiver with FS/LS backward compatibility
  • All USB Transfer Types – Interrupt, Bulk, Isochronous, and Control transfer support with prioritized scheduling for periodic endpoints and separate round-robin scheduling for non-periodic endpoints
  • Split Transaction Support – Split transfers for FS/LS devices connected to HS Hubs in Embedded Host Mode for complete USB 1.x device compatibility
  • Advanced Memory Management – Descriptor and data pre-fetch, pre-compute, and cache for optimized host controller memory access efficiency
  • High-Performance DMA Interface – DMA interface with configurable burst length for high-speed data transfers with direct AXI/AHB/APB register addressing
  • Robust Data Integrity – CRC16 generation and checking for HS data packets and CRC5 generation and checking for tokens
  • USB Power Management – USB Suspend state with remote wakeup and all HS USB Link Power Management states L1 and L2
  • System Power Management – System low power state support including Sleep, Hibernate, Warm Boot, and Cold Boot
  • Protocol Error Handling – Complete USB protocol layer error detection and handling for robust host controller operation
Compliance and Compatibility
  • Fully compliant with USB 2.0 specification (USB-IF); backward compatible with USB 1.1 and USB 1.0
  • Fully compliant with USB 2.0 Enhanced Host Controller Interface (EHCI) Revision 1.0
  • Compatible with UTMI v1.05 transceiver interface
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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