SmartDV’s USB 3.x Device IP is a silicon-proven, fully featured Universal Serial Bus SuperSpeed device solution purpose-built for SoC designs requiring high-performance USB device connectivity across embedded, automotive, AI/ML, and high-performance computing applications. Fully compliant with USB 3.0, 3.1, and 3.2 specifications, it delivers complete device-side USB functionality supporting SuperSpeed Gen1 at 5 Gbps, SuperSpeedPlus Gen2 at 10 Gbps, and dual-lane SuperSpeedPlus Gen2x2 at 20 Gbps — providing a proven, production-ready USB 3.x device interface for the most demanding embedded SoC designs.
Designed to address the full breadth of USB 3.x device integration requirements, the IP implements the complete USB 3.x feature progression from USB 3.0 ADP/HNP/SRP support through USB 3.1 SuperSpeedPlus LBPM, 128b/132b encoding, Precision Time Measurement, and transaction reordering, to USB 3.2 dual-lane operation, deskew buffer, data striping, and comprehensive retimer support including SRIS and Bit-Level Retimer functionality. Its configurable PIPE interface widths, scrambler/descrambler, all SS/SSP Link Power Management states U1/U2/U3, and complete system power management give SoC teams a production-tested, feature-complete USB 3.x device implementation covering the full USB 3.x specification evolution.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its configurable PIPE interface, Master and Slave loopback mode for PHY testing, and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.
