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Overview

SmartDV’s USB 3.x Verification IP is a comprehensive solution for verifying SuperSpeed USB interfaces, the high-bandwidth serial bus standard powering external storage, displays, docking stations, and high-throughput peripheral connectivity. Fully compliant with USB 3.0, USB 3.1, and USB 3.2 specifications, it supports complete verification of SuperSpeed USB 3.0, SuperSpeedPlus 3.1 and 3.2, and USB 3.0 OTG across comprehensive Host, Device, Hub, and PHY models, with configurable Configurations, Interfaces, Alternative Interfaces, and Endpoints, and configurable PHY interface widths of 8, 16, or 32 bits.

SmartDV’s USB 3.x VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With complete protocol, link, and physical layer compliance test suite coverage, Low Frequency Periodic Signaling for power management states U1, U2, and U3, eXtensible Host Controller Interface (xHCI) support, comprehensive error injection at all layers, built-in functional coverage, and a complete test suite, SmartDV’s USB 3.x VIP enables verification teams to thoroughly validate USB 3.x interface designs for SSD enclosures, docking stations, high-speed hubs, mobile and embedded SuperSpeed devices, and any application requiring USB 3.0, 3.1, or 3.2 connectivity.

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Key Features
  • Comprehensive USB 3.0/3.1/3.2 Common Support – Provides complete chip-level verification with comprehensive Host, Device, Hub, and PHY model support, configurable numbers of Configurations, Interfaces, Alternate Interfaces, and Endpoints, configurable PHY interface width of 8, 16, or 32 bits, PHY data scrambling for EMI reduction, separate Endpoint buffers for IN and OUT bound packets, lane polarity inversion, Bulk Stream support, and eXtensible Host Controller Interface (xHCI) support.
  • USB 3.0 Core and Super Speed Inter-Chip Coverage – Compliant with USB 3.0 specification and the USB 3.0 Super Speed Inter-Chip Supplement, supporting USB 3.0 Host and Device with SERIAL, PIPE, and SSIC interfaces, SS-OTG, SSPC-OTG, SS-PO, and SS-EH device types, ADP, HNP, SRP, and RSP protocols, and complete MIPI M-PHY Type-I operation including all PWM and HS gears, 1/2/4 lanes, RRAP packet types, and full M-PHY protocol error injection and detection.
  • USB 3.1 SuperSpeedPlus Coverage – Supports dual-simplex four-wire differential signaling with 128b/132b parallel interface, SuperSpeedPlus operation at 10 Gbit/s with backward compatibility to USB 3.0, USB 3.1 Host and Device with SERIAL/PIPE interfaces, specific LFPS patterns (SCD1/SCD2) for SuperSpeedPlus ports, SuperSpeedPlus LFPS Based PWM Message (LBPM), SuperSpeedPlus Precision Time Measurement, and SuperSpeedPlus Transaction Reordering for periodic and asynchronous packets.
  • USB 3.2 Dual-Lane Coverage – Supports dual-lane operation for Gen 1 and Gen 2 with full backward compatibility to USB 3.1 and USB 3.0, USB 3.2 Host and Device with dual-lane SERIAL/PIPE interface, Deskew buffer, data striping across dual lanes, dual-simplex four-wire differential signaling per lane with 128b/132b parallel interface, Configuration Summary Descriptor, link error count and soft error count tracking, and complete retimer connectivity models including all Retimer State Machine (RTSM) states, SRIS and bit-level retimer functionality, and retimer presence announcement through LBPM.
  • USB 3.0 OTG Coverage – Supports SS-OTG, SSPC-OTG, SS-PO, and SS-EH device types operating as USB 2.0 OTG equivalents, SRP, HNP, ADP, and RSP protocols at SS, HS, and FS speeds, feature selectors including b_hnp_enable, a_hnp_support, a_alt_hnp_support, NTF_HOST_REL, and B3_RSP_ENABLE, all defined timeout conditions, and combinations of SSPC-OTG and SS-OTG device communication including interoperation with USB 2.0 OTG devices.
  • Comprehensive Error Injection and Detection – Supports error injection and detection at all layers of USB 3.0, 3.1, and 3.2, on-the-fly protocol and data checking, and constrained randomization of protocol attributes for thorough robustness and fault tolerance verification.
  • Complete Verification Infrastructure – Provides a full test suite covering all USB 3.0, 3.1, and 3.2 specification features, built-in coverage analysis, and callbacks in host and device for user-defined event processing and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with USB 3.0, USB 3.1, and USB 3.2 specifications
  • Compliant with USB 3.0 SuperSpeed Inter-Chip Supplement (SSIC) using MIPI M-PHY
  • Supports SuperSpeed (5 Gbit/s), SuperSpeedPlus (10 Gbit/s), and USB 3.2 dual-lane (20 Gbit/s) operation
  • Supports 128b/132b and 8b/10b encoding across all supported generations
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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