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Overview

SmartDV’s USB 3.x OTG IP is a silicon-proven, fully featured Universal Serial Bus SuperSpeed On-The-Go solution purpose-built for SoC designs requiring flexible, dual-role USB connectivity across mobile, automotive, IoT, and high-performance embedded applications. Fully compliant with USB 3.0, 3.1, and 3.2 specifications and xHCI v1.0, it delivers a comprehensive USB 3.x OTG implementation supporting SS-OTG, SSPC-OTG, SS-PO, and SS-EH device types at SuperSpeed Gen1 (5 Gbps), SuperSpeedPlus Gen2 (10 Gbps), and dual-lane SuperSpeedPlus Gen2x2 (20 Gbps) — providing a proven, production-ready USB 3.x OTG solution for the most demanding embedded SoC designs.

Designed to address the full breadth of USB 3.x OTG integration requirements, the IP implements the complete OTG protocol suite including SRP, HNP, ADP, and RSP with comprehensive timeout condition handling, all OTG feature selectors, and full SSPC-OTG to SS-OTG device communication combinations. Its complete USB 3.x feature progression from USB 3.0 through USB 3.2 dual-lane operation, split transfer support for FS/LS devices in Embedded Host Mode, configurable downstream ports for Embedded Host applications, and comprehensive power management give SoC teams a production-tested, feature-complete USB 3.x OTG implementation suited for the most demanding mobile and embedded dual-role USB designs.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its configurable PIPE interface, xHCI-compliant host controller, and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.

Request Data Sheet
USB 3.x OTG
Key Features
  • Full USB 3.x OTG Functionality – Complete OTG implementation per USB 3.2 supporting SS-OTG, SSPC-OTG, SS-PO, and SS-EH device types at Gen1 (5 Gbps), Gen2 (10 Gbps), and Gen2x2 (20 Gbps) with HS and FS backward compatibility
  • Complete OTG Protocol Suite – SRP, HNP, ADP, and RSP for USB 3.0 with all OTG feature selectors including b_hnp_enable, a_hnp_support, a_alt_hnp_support, NTF_HOST_REL, and B3_RSP_ENABLE
  • Comprehensive OTG Timeout Management – Complete timeout condition handling including a_wait_vfall, a_wait_vrise, polling, recovery, rx_detect_active, rsp_cnf_err, rsp_ack_err, rsp_wrst, b3_polling, b3_recovery, and b3_rx_detect timeouts
  • SSPC-OTG Device Communication – SSPC-OTG to SSPC-OTG, SSPC-OTG to SS-OTG, and SS-OTG to SSPC-OTG device communication combinations
  • All USB Transfer Types – Interrupt, Bulk, Isochronous, and Control transfers with SS Bulk Streaming, High Bandwidth Interrupt and Isochronous endpoints, CRC32 for SS and CRC16/CRC5 for HS/FS/LS
  • SuperSpeedPlus Gen2 Features – LBPM, SCD1/SCD2 LFPS patterns, Precision Time Measurement, transaction reordering, Length field replica, Endpoint companion descriptor, and Type-A and Type-B credits
  • USB 3.2 Dual-Lane Features – Dual-lane operation with deskew buffer, data striping, Configuration summary descriptor, link and soft error count, and complete Retimer support including SRIS, Bit-Level Retimer, RTSM states, and Retimer presence announcement via LBPM
  • Embedded Host Features – Split Transfers for FS/LS devices via HS Hubs, LS preamble support, configurable downstream ports, and multiple SS/HS/FS hub device support
  • Comprehensive Power Management – SS/SSP LPM states U1/U2/U3, HS/FS LPM states L1/L2, USB 3.0 and USB 2.0 LPM transactions, USB Suspend with Remote Wakeup, and system Sleep/Hibernate/Warm/Cold Boot with clock gating and multi-power-well support
Compliance and Compatibility
  • Fully compliant with USB 3.2 specification; backward compatible with USB 3.1 and USB 3.0
  • Compliant with USB 3.0 OTG and Embedded Host specification
  • Compliant with xHCI Specification v1.0
  • Supports Gen1 (5 Gbps), Gen2 (10 Gbps), and Gen2x2 (20 Gbps) operating modes
  • Compatible with PIPE interface in 8, 16, and 32-bit widths
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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