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Overview

SmartDV’s USB 2.x Device IP is a silicon-proven, fully featured Universal Serial Bus device solution purpose-built for SoC designs requiring reliable, high-speed USB device connectivity across embedded, automotive, IoT, and consumer electronics applications. Fully compliant with USB 2.0, it delivers complete device-side USB functionality supporting High Speed (480 Mbps), Full Speed (12 Mbps), and Low Speed (1.5 Mbps) operation via UTMI transceivers in both 8-bit and 16-bit modes, with 16 bidirectional endpoints and integrated DMA controller functions — providing a proven, production-ready USB device interface for the most demanding embedded SoC designs.

Designed to address the full breadth of USB 2.x device integration requirements, the IP supports Interrupt, Bulk, Isochronous, and Control transfers including High Bandwidth Interrupt and Isochronous endpoints, three caching models for optimized memory access, descriptor and data pre-fetch and pre-compute, NAK counter for unnecessary memory access limiting, and Low Power Management with fsls serial mode. Its comprehensive error handling, USB Suspend with remote wakeup, clock gating with multi-power-well support, and system low power state management give SoC teams a production-tested, feature-complete USB 2.x device implementation optimized for power-sensitive embedded applications.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its UTMI 8-bit and 16-bit interface support and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.

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USB 2.x Device
Benefits
  • Full USB 2.x Device FunctionalityComplete device-side USB 2.0 implementation supporting HS (480 Mbps), FS (12 Mbps), and LS (1.5 Mbps) operation via UTMI 8-bit and 16-bit transceiver interfaces
  • All USB Transfer Types – Interrupt, Bulk, Isochronous, and Control transfers with High Bandwidth Interrupt and Isochronous endpoint support and 16 bidirectional endpoints
  • Advanced Memory Management – Three caching models (no caching, micro-frame caching, and frame caching), descriptor and data pre-fetch/pre-compute/cache, and NAK counter for optimized memory access
  • Integrated DMA Controller – Built-in DMA controller functions for efficient, processor-offloaded USB data transfer management
  • Robust Data Integrity – CRC16 generation and checking for HS/FS/LS data packets and CRC5 generation and checking for tokens
  • USB Power Management – USB Suspend state with remote wakeup, Low Power Management, fsls serial mode, and all USB 2.0 Link Power Management states
  • System Power Management – System low power state support including Sleep, Hibernate, Warm Boot, and Cold Boot with clock gating and multi-power-well support
  • Protocol Error Handling – Complete USB protocol layer error detection and handling for robust device operation
Compliance and Compatibility
  • Fully compliant with USB 2.0 specification (USB-IF); backward compatible with USB 1.1 and USB 1.0
  • Compatible with UTMI v1.05 transceiver interface in 8-bit and 16-bit modes
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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