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Overview

SmartDV’s USB PD IP is a silicon-proven, fully featured USB Power Delivery solution purpose-built for SoC designs requiring complete PD MAC and protocol layer implementation for USB Type-C power management across mobile, automotive, IoT, and consumer electronics applications. Fully compliant with USB Power Delivery Specification Revision 3.2 and USB Type-C Cable and Connector Specification Release 2.4, it delivers complete BMC-based PD MAC transmit and receive functionality alongside a comprehensive PD Protocol Layer with hardware-implemented Policy Engine sequences, supporting USB 3.2 and USB4 data interfaces and up to 240W Extended Power Range operation.

Designed to address the full breadth of USB PD integration requirements, the IP implements a complete PD MAC layer covering BMC encoding and decoding, SOP* detection, CRC32 generation and validation, Hard Reset and Cable Reset ordered set generation and detection, and BIST frame support — alongside a fully featured PD Protocol Layer with hardware-autonomous message handling, programmable PD timers, standard retry mechanisms, and firmware interrupt support. Its AHB Slave 32/64-bit interface, programmable tInterframeGap, and BMC to PHY interface give SoC teams a production-tested, spec-complete USB PD implementation that handles the complete USB PD message flow from physical layer encoding to protocol policy execution.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture, hardware Policy Engine implementation with firmware support, and clean AHB host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.

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USB PD
Benefits
  • Full USB PD MAC Layer Transmitter – BMC encoding, 32-bit CRC generation and appending, SOP* ordered set generation, Hard Reset, Cable Reset, and SOP_Debug ordered set generation, programmable tInterframeGap, and BIST frame generation with BMC signaling patterns
  • Full USB PD MAC Layer Receiver – BMC clock recovery and packet lock from preamble, SOP* detection, BMC decoding, 32-bit CRC validation, EOP detection, Hard Reset/Cable Reset/SOP_Debug ordered set detection, and BIST frame reception
  • Complete PD Protocol Layer – All Control and Data Message Transfer Sequences with hardware-autonomous message generation, firmware interrupt on successful transmit/receive, standard retry mechanisms, and fully programmable PD Protocol Timers
  • Hardware Policy Engine – All Policy Engine related sequences implemented in hardware with firmware support for complete, standards-compliant USB PD policy execution
  • USB 3.2 and USB4 Support – Data interface compatibility with USB 3.2 and USB4 for comprehensive high-speed data and power delivery integration
  • BMC to PHY Interface – Direct BMC bitstream interface to third-party external Analog Front End/PHY for flexible physical layer integration
  • AHB Slave Interface – 32/64-bit AHB Slave interface for register programming and seamless SoC integration
Compliance and Compatibility
  • Fully compliant with USB Power Delivery Specification Revision 3.2 Version 1.2; backward compatible with Revision 3.1 and 3.0
  • Compliant with USB Type-C Cable and Connector Specification Release 2.4; backward compatible with Release 3.0 and 2.0
  • Compatible with USB 3.2 and USB4 data interfaces
  • Configurable SoC interface supporting AMBA AHB, AXI, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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