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Overview

SmartDV’s USB 1.x Device IP is a silicon-proven, fully featured Universal Serial Bus device solution purpose-built for SoC designs requiring reliable, standards-compliant USB device connectivity across embedded, automotive, IoT, and consumer electronics applications. Fully compliant with USB 1.1, it delivers complete device-side USB functionality supporting both Low Speed (1.5 Mbps) and Full Speed (12 Mbps) operation via UTMI and ULPI transceivers, with support for all USB transfer types and comprehensive power management — providing a proven, production-ready USB device interface for a wide range of embedded and consumer SoC designs.

Designed to address the full breadth of USB 1.x device integration requirements, the IP supports Interrupt, Bulk, Isochronous, and Control transfers, CRC16 and CRC5 generation and checking, prioritized scheduling for periodic endpoints, separate round-robin scheduling for periodic and non-periodic endpoint pipes, and USB Suspend with remote wakeup. Its support for all FS USB Link Power Management states L1 and L2, system low power states including Sleep, Hibernate, Warm and Cold boot, and clock gating with multi-power-well support gives SoC teams a production-tested, spec-complete USB 1.x device implementation optimized for power-sensitive embedded applications.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its UTMI and ULPI transceiver interface support and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.

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USB 1.x Device
Benefits
  • Full USB 1.x Device FunctionalityComplete device-side USB implementation per USB 1.1 supporting LS (1.5 Mbps) and FS (12 Mbps) operation via UTMI and ULPI transceivers
  • All USB Transfer Types – Interrupt, Bulk, Isochronous, and Control transfer support for complete USB device protocol coverage
  • Robust Data Integrity – CRC16 generation and checking for FS/LS data packets and CRC5 generation and checking for tokens
  • Prioritized Endpoint SchedulingPrioritized scheduling for periodic endpoints with separate round-robin scheduling for periodic and non-periodic endpoint pipes
  • USB Power Management – USB Suspend state with remote wakeup support and all FS USB Link Power Management states L1 and L2
  • System Power Management – System low power state support including Sleep, Hibernate, Warm Boot, and Cold Boot with clock gating and multi-power-well support
  • LS Preamble Support – Preamble support for LS transfers while operating in Host Mode for complete USB 1.1 topology compatibility
  • Protocol Error Handling – Complete USB protocol layer error detection and handling for robust device operation
Compliance and Compatibility
  • Fully compliant with USB 1.1 specification (USB-IF)
  • Compatible with UTMI v1.05 and ULPI Revision 1.1 transceiver interfaces
  • Configurable SoC interface supporting AMBA AXI, AHB, APB, and custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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