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Overview

SmartDV’s USB PD verification IP enables fast testbench development and verification signoff of USB Power Delivery hardware IP integrated in FPGAs, ASICs, and SoCs.

Benefits
Deployed for the verification of silicon-proven IP cores
Comprehensive library of constrained random sequences and test suite
Protocol checks, functional coverage, verification plan
Easy to instantiate and configure
Enables quick debug and root-cause analysis of RTL bugs
Error detection and insertion
Compliance and Compatibility
USB Power Delivery Specification
Runs in all major simulation environments
UVM, SystemVerilog, OVM, Specman, and other verification languages and methodologies