SmartDV’s USB 3.x Host IP is a silicon-proven, fully featured Universal Serial Bus SuperSpeed host controller solution purpose-built for SoC designs requiring high-performance USB host connectivity across embedded, automotive, AI/ML, and high-performance computing applications. Fully compliant with USB 3.0, 3.1, and 3.2 specifications and xHCI v1.0, it delivers complete host-side USB functionality supporting SuperSpeed Gen1 at 5 Gbps, SuperSpeedPlus Gen2 at 10 Gbps, and dual-lane SuperSpeedPlus Gen2x2 at 20 Gbps with USB 3.0 OTG support, providing a proven, production-ready USB 3.x host controller for the most demanding embedded SoC designs.
Designed to address the full breadth of USB 3.x host integration requirements, the IP implements the complete USB 3.x feature progression from USB 3.0 ADP/HNP/SRP support through USB 3.1 SuperSpeedPlus LBPM, 128b/132b encoding, Precision Time Measurement, and transaction reordering, to USB 3.2 dual-lane operation, deskew buffer, data striping, and comprehensive retimer support including SRIS and Bit-Level Retimer functionality. Its xHCI-compliant host controller implementation, configurable PIPE interface widths, LFPS signaling and SCD/LBPM messaging, all SS/SSP Link Power Management states U1/U2/U3, and complete system power management give SoC teams a production-tested, feature-complete USB 3.x host controller covering the full USB 3.x specification evolution.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its configurable PIPE interface, Master and Slave loopback mode for PHY testing, and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.
