SmartDV’s AXI to UCIe Bridge IP is a silicon-proven, fully featured chiplet interconnect bridge solution purpose-built for SoC and multi-die system designs requiring seamless AXI streaming protocol transport over Universal Chiplet Interconnect Express die-to-die links. Fully compliant with UCIe v3.0 and backward compatible with UCIe v2.0, v1.1, and v1.0, and compliant with ARM AMBA AXI5 (backward compatible with AXI4 and AXI3), it enables AXI streaming protocol traffic to traverse UCIe die-to-die interconnects at speeds up to 64 GT/s, with data bus widths from 8 to 1024 bits and lane configurations of 16, 32, and 64 lanes.
Designed for AI accelerator, HPC chiplet, and data center multi-die architectures where AXI-connected chiplets must communicate efficiently over UCIe streaming protocol links, the IP supports Standard and Advanced Package configurations, all UCIe FLIT formats for streaming protocols, UCIe clock frequencies from 500 MHz to 8 GHz, and the complete UCIe sideband infrastructure including Sideband Mailbox, Retimer support, FLIT Retry, FLIT CRC, and all Vendor Defined Sideband messages. Its two available core variants supporting multiple outstanding requests with simultaneous read/write channel access or single-channel sequential access give chiplet system teams flexible implementation options for diverse AXI streaming use cases.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations. Its parameterized lane architecture and clean host interface enable fast integration across a wide range of advanced process nodes and chiplet packaging configurations.
