SmartDV’s AMBA AXI5 Verification IP is a comprehensive solution for verifying high-performance, high-frequency interconnect designs based on the Arm AMBA 5 AXI architecture. Fully compliant with the AMBA AXI Protocol Specification Issue L and backward compatible with AXI4, AXI4-Lite, and AXI3, it supports complete verification of AXI5 Master, Slave, Monitor, and Checker components across all data and address widths, covering all transfer types, burst types, burst lengths up to 256 beats, burst sizes, and response types, along with the full suite of AXI5-specific features including atomic transactions, data check, poison, QoS Accept, trace signals, user loopback, wake-up signaling, untranslated transactions, and Non-Secure Access Identifiers.
SmartDV’s AMBA AXI5 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With fine-grain Master and Slave control, extensive error injection, interface parity protection, Memory Tagging Extensions, Memory Partitioning and Monitoring, on-the-fly protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s AMBA AXI5 VIP enables verification teams to thoroughly validate high-bandwidth interconnect designs for mobile, automotive, networking, AI, and high-performance computing applications.
