SmartDV’s AMBA AHB5 Verification IP is a comprehensive solution for verifying Advanced High-performance Bus designs based on the Arm AMBA 5 architecture. Fully compliant with the AMBA AHB5 specification Issue C and backward compatible with AHB-Lite and AHB (AMBA 3), it supports complete verification of AHB5 Master, Slave, Monitor, and Checker components, covering all transfer types, burst transfers, response types, and transfer sizes, including ARM11 extensions, across all supported data and address widths.
SmartDV’s AMBA AHB5 VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With fine-grain control of Master and Slave behavior, locked and exclusive transfer support, split and retry handling, error injection, interface parity protection, TrustZone security signaling, on-the-fly protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s AMBA AHB5 VIP enables verification teams to thoroughly validate embedded bus interconnect designs for mobile, automotive, IoT, and low-latency SoC applications.
