SmartDV’s AMBA CHI Verification IP is a comprehensive solution for verifying fully coherent interconnect designs based on the Arm AMBA 5 Coherent Hub Interface architecture. Fully compliant with the AMBA 5 CHI Architecture Specification Issue G and backward compatible with Issues B through F, it supports complete verification of all CHI node types including Request Nodes (RN-F, RN-D, and RN-I), Home Nodes (HN-F, HN-I, and MN), and Slave Nodes (SN-F and SN-I), across Protocol, Network, and Link layers with full flow control mechanisms for RN-to-HN and HN-to-SN links.
SmartDV’s AMBA CHI VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With programmable cache models, speculative read and snoop filtering support, Direct Memory Transfer and Direct Cache Transfer, extensive error injection, fine-grain control across all node types, transaction logging and performance reporting, on-the-fly protocol and system level checking, built-in functional coverage, and a complete test suite, SmartDV’s AMBA CHI VIP enables verification teams to thoroughly validate high-performance coherent interconnect designs for mobile, automotive, AI, data center, and high-performance computing applications.
