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Overview

SmartDV’s AMBA CXS Verification IP is a comprehensive solution for verifying the Credited eXtensible Streaming interface, a point-to-point packetized communication protocol optimized for the transport of CCIX and CXL packets between on-chip interconnects and PCIe controllers. Fully compliant with the AMBA CXS Protocol Specification Version D and backward compatible with earlier issues, it supports complete verification of CXS Transmitter, Receiver, Monitor, and Checker components, covering credit exchange mechanisms, link activation and deactivation, continuous data delivery, and fine-grain control of flit packet placement and packet control fields across all configurable interface widths.

SmartDV’s AMBA CXS VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With configurable dynamic and pre-allocated credit control, extensive error injection across all protocol layers, programmable signal delays, transaction logging and performance reporting, on-the-fly protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s AMBA CXS VIP enables verification teams to thoroughly validate streaming interface designs for CCIX, CXL, and PCIe bridging applications in high-performance computing, data center, and AI SoC environments.

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AMBA CXS VIP
Benefits
  • Full CXS Agent Support – Provides Transmitter, Receiver, Monitor, and Checker components with support for all configurable interface signal widths, interface properties and options as per protocol, and a rich set of configuration parameters for fine-grain CXS protocol control.
  • Credit Exchange and Flow Control – Supports the full credit exchange mechanism with configurable dynamic and pre-allocated credit control, continuous delivery of data for uninterrupted packet transmission, and fine-grain control of flit packet placement and packet control fields.
  • Link Activation and Deactivation – Supports link activation and deactivation as per specification, with support for skipping link activation, error injection during link activation and deactivation sequences, and programmable protocol signal delays.
  • Comprehensive Error Injection and Detection – Supports injection and detection of errors across all CXS protocol elements including credit exchange mechanism, flit packet placement, parity, packet control fields, packet size, and link activation and deactivation sequences.
  • Robust Protocol Checking and Monitoring – Provides on-the-fly protocol and data checking, programmable timeout insertion, status counters for bus events, transaction logging and performance reporting, and notification of significant events including transactions, warnings, and protocol and timing violations.
  • Complete Verification Infrastructure – Provides built-in functional coverage analysis, constraints randomization, and callbacks in Transmitter, Receiver, and Monitor for user-defined event handling across all CXS protocol conditions.
Compliance and Compatibility
  • Fully compliant with Arm AMBA CXS Protocol Specification Version D; backward compatible with earlier issues
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

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