SmartDV’s AMBA LPI Verification IP is a comprehensive solution for verifying the Low Power Interface protocol, designed to manage clock and power features of SoC components through Q-Channel and P-Channel interfaces. Fully compliant with the AMBA Low Power Interface Specification Version D and backward compatible with earlier issues, it supports complete verification of LPI Controller, Device, Monitor, and Checker components, covering Q-Channel for autonomous hierarchical clock gating and simple component power control, and P-Channel for more complex power control features, with full handshake mechanism verification, quiescent state entry and exit, and configurable active and deny interface support.
SmartDV’s AMBA LPI VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With interface parity protection, configurable active and deny interfaces, programmable wait states and timeouts, error injection, on-the-fly protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s AMBA LPI VIP enables verification teams to thoroughly validate low-power clock and power management interfaces for mobile, automotive, IoT, and low-power embedded SoC applications.
