SmartDV’s AMBA ATB Verification IP is a comprehensive solution for verifying the Advanced Trace Bus interface across all generations of the Arm AMBA ATB specification. Fully compliant with the AMBA ATB specification Issue C (AMBA 5) and backward compatible with ATBv1.1 (AMBA 4) and ATBv1.0 (AMBA 3), it supports complete verification of ATB Master, Slave, Monitor, and Checker components across all ATB data, byte, and ID widths, covering all trace data transfer types, flow control signaling, flush request handling, synchronization, and trace triggering operations.
SmartDV’s AMBA ATB VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With support for multiple masters and slaves, programmable trace IDs, master internal buffer storage, error injection, wake-up signaling, on-the-fly protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s AMBA ATB VIP enables verification teams to thoroughly validate CoreSight trace infrastructure designs for mobile, automotive, and embedded SoC debug and trace applications.
