SmartDV’s AMBA AXI-Stream Verification IP is a comprehensive solution for verifying unidirectional high-speed streaming data interfaces based on the Arm AMBA AXI-Stream architecture. Fully compliant with the AMBA AXI-Stream Protocol Specification Issue B (AXI5-Stream) and backward compatible with AXI4-Stream, it supports complete verification of AXI-Stream Master, Slave, Monitor, and Checker components across all data widths, covering all stream types including byte streams, continuous aligned streams, continuous unaligned streams, and sparse streams, with support for single byte, packet, and frame transfers, transfer interleaving, and upsizing, downsizing, and merging operations.
SmartDV’s AMBA AXI-Stream VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With fine-grain Slave control, programmable wait states, error injection, interface parity protection, wake-up signaling, on-the-fly protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s AMBA AXI-Stream VIP enables verification teams to thoroughly validate streaming data interconnect designs for multimedia, networking, AI, and high-performance embedded SoC applications.
