SmartDV’s AMBA ACE5 and ACE5-Lite Verification IP is a comprehensive solution for verifying cache coherent and I/O coherent interconnect designs based on the Arm AMBA 5 architecture. Fully compliant with the AMBA AXI and ACE Protocol Specification Issue L and backward compatible with ACE and ACE-Lite (AMBA 4), it supports complete verification of ACE5 Master, Slave, Interconnect, Monitor, and Checker components, covering all transaction types including Snoop, Evict, WriteEvict, Barrier, and Distributed Virtual Memory transactions, alongside all ACE5-Lite transaction types including shareable, non-shareable, and broadcast cache maintenance operations.
SmartDV’s AMBA ACE5 and ACE5-Lite VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With fine-grain control of Master, Slave, and Interconnect behavior, extensive error injection, atomic transaction support, cache stashing, interface parity protection, on-the-fly protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s AMBA ACE5 and ACE5-Lite VIP enables verification teams to thoroughly validate cache coherent SoC interconnect designs for mobile, automotive, networking, and high-performance computing applications.
