SmartDV’s PCIe Verification IP is a comprehensive solution for verifying the PCI Express high-speed serial interconnect across all defined generations for AI accelerators, data center infrastructure, storage, networking, automotive, and embedded computing applications. Fully compliant with PCI Express 7.0 (June 2025) and backward compatible through PCIe 6.0, 5.0, 4.0, 3.0, 2.1, 2.0, and 1.0, it supports complete verification of PCIe Root Complex and Endpoint components across configurable link widths from x1 to x32, PIPE, PCS/PMA, Message Bus, and SerDes interfaces, all defined encoding schemes from 8b/10b through 128b/130b to 1b/1b, Flit and non-Flit modes, PAM4 signaling, Forward Error Correction, all power management states including L0p, 8 virtual channels, SR-IOV, IDE, DOE, and the full PCIe protocol stack across transaction, data link, and physical layers.
SmartDV’s PCIe VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With full LTSSM and DLL state machines, automated error injection at all layers, Lane Margining at Receiver, Shared Credit Pool, Link Management DLLP, Gray coding and Precoding, Spread Spectrum Clocking, up-configure, polarity inversion, lane skew, built-in functional coverage, and a complete test suite, SmartDV’s PCIe VIP enables verification teams to thoroughly validate PCIe interface designs for AI accelerators, data center switches, NVMe SSDs, GPUs, network adapters, automotive SoCs, and high-performance computing platforms.
