SmartDV’s PCIe 5.0 Controller IP is a high-performance PCI Express interconnect solution purpose-built for SoC designs requiring extreme bandwidth connectivity across AI/ML accelerators, high-performance computing, and next-generation data center applications. Fully compliant with the PCI-SIG PCIe 5.0 specification, it delivers complete Root Complex and Endpoint controller functionality at 32 GT/s per lane with 128b/130b encoding and support for link widths up to x16, providing a feature-complete PCIe interconnect foundation capable of up to 128 GB/s bidirectional throughput in an x16 configuration.
Engineered for the extreme bandwidth and signal integrity demands of AI accelerator and HPC interconnect designs, the IP implements the complete LTSSM state machine, data scrambling, full link speed and width negotiation, and a comprehensive transaction layer supporting up to 8 Virtual Channels and 8 Traffic Classes. Currently FPGA proven and targeting silicon validation, it gives SoC teams early access to a spec-complete PCIe 5.0 controller implementation for platform bring-up and system validation ahead of production deployment.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its PIPE interface compatibility, up to 40-bit SerDes width support, and comprehensive power management feature set enable fast integration and confident design bring-up across a wide range of advanced process nodes and target applications.
