SmartDV’s PCIe 6.0 Controller IP is a next-generation PCI Express interconnect solution engineered for the most demanding SoC applications in AI/ML accelerators, high-performance computing, and data center infrastructure. Fully compliant with the PCI-SIG PCIe 6.0 specification, it delivers complete Root Complex and Endpoint controller functionality at 64 GT/s per lane using PAM4 signaling with FLIT-based encoding, achieving up to 256 GB/s bidirectional throughput in an x16 configuration — doubling the bandwidth of PCIe 5.0 while maintaining full backward compatibility across all previous PCIe generations.
As the most bandwidth-intensive PCIe generation to date, PCIe 6.0 introduces significant architectural advances including FLIT mode operation, lightweight Forward Error Correction, and PAM4 modulation that together deliver unprecedented throughput with minimal latency overhead. SmartDV’s PCIe 6.0 Controller IP implements the complete feature set of these advances — including both FLIT and Non-FLIT mode support, 40B SKIP ordered sets, FLIT CRC and FEC, and the full PCIe 6.0 power management suite — giving SoC teams a spec-complete, future-ready PCIe interconnect implementation for next-generation AI and data center platform designs.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its PIPE interface compatibility, up to 40-bit SerDes width support, and comprehensive FLIT mode architecture enable fast integration and confident design bring-up across a wide range of advanced process nodes and target applications.
