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Overview

SmartDV‘s PCIe Synthesizable Transactor is a fully featured PCI Express bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable PCIe Root Complex and Endpoint behavior during pre-silicon validation of embedded, automotive, AI/ML, HPC, and data center SoC designs. Fully compliant with PCI-SIG PCIe 6.0 and backward compatible with PCIe 5.0, 4.0, 3.1, 2.1, and 1.0, it delivers complete Root Complex and Endpoint functionality across all PCIe generations from Gen1 at 2.5 GT/s through Gen6 at 64 GT/s with PAM4 signaling, giving validation teams a single drop-in synthesizable PCIe transactor spanning the full range of PCIe protocol generations used in modern SoC designs.

Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports complete LTSSM state machine modeling, speed and link width negotiation, lane polarity inversion and reversal detection and correction, FLIT and Non-FLIT mode operation, all TLP types with header, prefix, and ECRC validation, DLLP field checking, scaled flow control, data link feature exchange, up to 8 Virtual Channels and 8 Traffic Classes, and the full PCIe power management suite, enabling validation teams to exercise corner-case PCIe behavior that is difficult to reach with production RTL alone.

Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its comprehensive error injection suite, programmable timeout insertion, lane margining support, and testbench notification of significant events, warnings, timing, and protocol violations enable rapid deployment for early software bring-up and PCIe system-level validation regardless of the underlying emulation platform.

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PCIe Transactor
Key Features
  • Full PCIe Root Complex and Endpoint Model – Complete Root Complex and Endpoint behavior per PCI-SIG PCIe 6.0 covering Gen1 (2.5 GT/s) through Gen6 (64 GT/s, PAM4) with link widths up to x16
  • Complete LTSSM State Machine – Full Link Training and Status State Machine modeling with speed and link width negotiation, lane polarity inversion, lane reversal detection and correction, and Up Configure support
  • FLIT and Non-FLIT Mode Support – Both FLIT mode and Non-FLIT mode operation with 40B SKIP ordered set support and FLIT CRC and FEC for Gen6 PAM4 validation
  • Comprehensive Transaction Layer – All TLP types with header and prefix validation, ECRC support, up to 8 Virtual Channels with configurable depth queuing, up to 8 Traffic Classes, configurable TC to VC mapping, and multi-function support
  • Robust Data Integrity – LCRC, DLLP field checking, TLP header and prefix validation, ECRC, FLIT CRC and FEC, and retry mechanism for reliable PCIe transaction validation
  • Advanced Power Management Modeling – ASPM, software-controlled power management, Link Power Management, L1 PM Sub-states, and Emergency Power Reduction State for complete power state validation
  • Lane Margining at Receiver – Hardware lane margining support for signal integrity validation at high-speed PCIe operating speeds
  • Error and Timing Injection – Programmable timer and timeout insertion, error injection during transfers, and data scrambling for Gen3 through Gen6 for comprehensive PCIe stress testing
  • On-the-Fly Protocol Checking – Real-time protocol and data checking with testbench notification of significant events, warnings, timing, and protocol violations
Compliance and Compatibility
  • Fully compliant with PCI-SIG PCIe 6.0; backward compatible with PCIe 5.0, 4.0, 3.1, 2.1, and 1.0
  • Supports PIPE interface for PHY integration with up to 32-bit pipe width and up to 40-bit SerDes width
  • Fully synthesizable and platform-independent, deployable on any hardware emulation or FPGA prototyping platform
  • Vendor-agnostic integration suitable for Synopsys, Cadence, Siemens, and custom emulation and prototyping environments
  • Configurable interface supporting integration into custom emulation and prototyping testbenches

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