SmartDV’s CHI to UCIe Bridge IP is a fully featured chiplet interconnect bridge solution purpose-built for SoC and multi-die system designs requiring seamless AMBA 5 CHI coherency protocol transport over Universal Chiplet Interconnect Express die-to-die links. Fully compliant with UCIe v3.0 and backward compatible with UCIe v2.0, v1.1, and v1.0, and compliant with the latest ARM AMBA 5 CHI Architecture Specification, it enables CHI protocol traffic across all node types including Request Nodes (RN-F, RN-D, RN-I), Home Nodes (HN-F, HN-I, MN), and Slave Nodes (SN-F, SN-I) to traverse UCIe die-to-die interconnects at speeds up to 64 GT/s across 16, 32, and 64 lane configurations.
Designed for AI accelerator, HPC chiplet, and data center multi-die architectures requiring coherent die-to-die communication, the IP implements the complete CHI Protocol, Network, and Link layer stack across RN-to-HN and HN-to-SN links, configurable dynamic and pre-allocated credit control, cache model support in both master and interconnect, speculative read and snoop filtering, all CHI transaction types and opcodes, Direct Memory Transfer, Direct Cache Transfer, DVM operations, exclusive accesses, cache stashing, and data poisoning. Its FIFO memory support, interconnect ability to replicate RN/SN delays, and fine-grain control of all CHI node transaction types give chiplet system teams a spec-complete CHI-to-UCIe bridge implementation.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations. Its parameterized lane architecture and clean host interface enable fast integration across a wide range of advanced process nodes and chiplet packaging configurations.
