SmartDV’s AMBA CHI AIP is a fully featured SVA-based formal verification IP purpose-built for SoC designs requiring exhaustive, property-driven verification of AMBA 5 CHI coherency protocol compliance across fully coherent CPU subsystems, cache interconnects, and multi-chip interconnect designs. Covering all standard CHI node types including RN-F, RN-D, RN-I, SN-F, and SN-I, it delivers a comprehensive set of SystemVerilog Assertions targeting the full breadth of CHI protocol rules including transaction ordering, coherency state machine correctness, credit management, Direct Memory Transfer, Direct Cache Transfer, DVM operation sequencing, and exclusive access semantics.
Designed to complement simulation-based verification with the exhaustive state space exploration that only formal methods can provide, the AIP targets the class of subtle CHI coherency bugs including illegal state transitions, credit exhaustion, ordering violations, snoop filter inconsistencies, and DVM sequencing errors that are statistically unlikely to surface in directed or constrained-random simulation but can cause catastrophic system failures in high-performance CPU subsystem silicon. Its parameterized constraint and assumption architecture allows formal tools to focus verification effort on the most critical protocol properties while bounding the state space to tractable problem sizes.
Compatible with industry-standard formal verification tools and fully independent of any specific EDA vendor platform, the AIP integrates cleanly into existing formal flows with minimal setup overhead. Its modular property organization across Protocol, Network, and Link layers, configurable protocol parameters, and clear assertion naming conventions enable verification teams to rapidly deploy, customize, and extend the property set to match the specific CHI configuration and design context of their SoC.
