SmartDV’s UCIe Verification IP is a comprehensive solution for verifying Universal Chiplet Interconnect Express, the open industry standard die-to-die interconnect enabling multi-vendor chiplet interoperability at the package level across physical layer, protocol, and software stack. Fully compliant with UCIe Specification Versions 1.0, 1.1, 2.0, and 3.0, it supports complete verification of UCIe Die-0 and Die-1 components across Standard Package (x16 with x8 width degrade) and Advanced Package (x32, x64) configurations, continuous and strobe half-rate clocking modes, and mapped protocols including PCIe, CXL, and AXI Streaming Protocol.
SmartDV’s UCIe VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With complete Flit format coverage, speeds from 4 GT/s through 64 GT/s, full LTSSM state machine, sideband mailbox mechanism, Flit retry and error recovery, lane repair and reversal, comprehensive error injection at all layers, built-in functional coverage, and a complete test suite, SmartDV’s UCIe VIP enables verification teams to thoroughly validate UCIe interface designs for chiplet-based SoCs, AI accelerators, high-performance computing platforms, and any multi-die System-in-Package requiring open, interoperable die-to-die connectivity.
