SmartDV’s UCIe 2.x Controller IP is a silicon-proven, fully featured Universal Chiplet Interconnect Express solution purpose-built for SoC and multi-die system designs requiring high-bandwidth, low-latency die-to-die connectivity across AI accelerators, high-performance computing, and data center chiplet architectures. Fully compliant with UCIe v2.0 and backward compatible with UCIe v1.1 and v1.0, it delivers complete UCIe controller functionality supporting PCIe, CXL, and streaming protocols including AXI, CXS, and CHI at speeds up to 32 GT/s across 16, 32, and 64 lane configurations, providing a proven, production-ready die-to-die interconnect foundation for demanding chiplet-based system designs.
Designed to address the full breadth of UCIe controller requirements, the IP implements the complete UCIe stack spanning the Protocol Layer with AXI, CXL, CXS, PCIe, and CHI bridges, D2D Adapter Layer with Flit Pack, Flit Retry, CRC, and Parity, and APB Sideband with Protocol and Credit management. Its support for both Standard and Advanced Package configurations, all six UCIe FLIT formats, UCIe Retimers, Multi-Stack protocol, and comprehensive sideband infrastructure including Sideband Mailbox and all Vendor Defined Sideband messages gives chiplet system teams a production-tested, spec-complete UCIe controller that integrates cleanly into the most demanding multi-die architectures.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized lane architecture, clock gating mechanism, and RDI TX/RX interface to the PHY enable fast integration and confident design bring-up across a wide range of advanced process nodes and chiplet packaging configurations.