SmartDV’s PCIe to UCIe Bridge IP is a next-generation chiplet interconnect solution engineered for SoC and multi-die system designs requiring seamless, high-bandwidth bridging between PCI Express and Universal Chiplet Interconnect Express fabrics. Fully compliant with UCIe v3.0 and PCI-SIG PCIe 6.0, it enables PCIe protocol traffic to traverse UCIe die-to-die interconnects at speeds up to 64 GT/s, making it a strategic choice for AI accelerators, HPC chiplet systems, and data center multi-die architectures where PCIe-connected chiplets must communicate efficiently across standard and advanced packaging configurations.
As the semiconductor industry accelerates its transition from monolithic SoCs to modular chiplet-based architectures, the need for a standards-compliant PCIe-to-UCIe bridge has become critical. SmartDV’s Bridge IP addresses this with support for both Standard and Advanced Package configurations, all six UCIe FLIT formats, lane widths from 16 to 64 lanes, UCIe clock frequencies from 500 MHz to 8 GHz, and the complete UCIe sideband infrastructure including mailbox messaging, retimer support, and runtime recalibration — giving chiplet system teams a complete, production-ready bridge solution that eliminates the complexity of custom protocol translation.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture, configurable clock gating, and clean host interface enable fast integration and confident design bring-up across a wide range of advanced process nodes and chiplet packaging configurations.
