SmartDV’s CXS to UCIe Bridge IP is a fully featured chiplet interconnect bridge solution purpose-built for SoC and multi-die system designs requiring seamless AMBA CXS streaming protocol transport over Universal Chiplet Interconnect Express die-to-die links. Fully compliant with UCIe v3.0 and backward compatible with UCIe v2.0, v1.1, and v1.0, and compliant with the latest ARM AMBA CXS specification, it enables CXS streaming protocol traffic to traverse UCIe die-to-die interconnects at speeds up to 64 GT/s across 16, 32, and 64 lane configurations with Standard and Advanced Package support.
Designed for AI accelerator, HPC chiplet, and data center multi-die architectures requiring high-bandwidth CXS streaming die-to-die communication, the IP implements the complete CXS protocol stack over UCIe including credit exchange mechanism, link activation and deactivation with optional skip, configurable dynamic and pre-allocated credit control, continuous delivery of uninterrupted packet transmission, fine-grain control of flit packet placement and control fields, all interface properties and options per CXS specification, comprehensive error injection and detection, and the complete UCIe sideband infrastructure.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations. Its parameterized lane architecture and clean host interface enable fast integration across a wide range of advanced process nodes and chiplet packaging configurations.
