SmartDV’s CXL to UCIe Bridge IP is a fully featured chiplet interconnect bridge solution purpose-built for SoC and multi-die system designs requiring seamless CXL protocol transport over Universal Chiplet Interconnect Express die-to-die links. Fully compliant with UCIe v3.0 and backward compatible with UCIe v2.0, v1.1, and v1.0, and compliant with CXL 2.0/3.0/3.1/3.2, it enables CXL.io, CXL.cache, and CXL.mem protocol traffic to traverse UCIe die-to-die interconnects at speeds up to 64 GT/s across 16, 32, and 64 lane configurations with Standard and Advanced Package support.
Designed for AI accelerator, HPC chiplet, and data center multi-die architectures requiring coherent CXL die-to-die communication, the IP implements the complete CXL protocol stack over UCIe including all CXL.cache/CXL.mem request and response messages, snoop responses, 32B and 64B cache line support, Standard 256B Start Header FLIT formats for both CXL.io and CXL.cache/CXL.mem, Standard 256B End Header FLIT format, ARB/MUX Link Management Packets, Multiple Data Header, byte enable, link layer retry, and data poisoning, alongside the complete UCIe sideband infrastructure.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations. Its parameterized lane architecture and clean host interface enable fast integration across a wide range of advanced process nodes and chiplet packaging configurations.
