SmartDV’s CXL 1.x Controller IP is a fully featured Compute Express Link solution purpose-built for SoC designs requiring high-bandwidth, cache-coherent connectivity in AI accelerator, HPC, and data center applications. Compliant with CXL 1.0 and 1.1 specifications and built on the PCIe 5.0 physical interface, it delivers complete CXL.io, CXL.cache, and CXL.mem protocol implementations with native PCIe mode support, full ARB/MUX functionality, and support for CXL Type 1, Type 2, and Type 3 devices at 32 GT/s signaling rates.
Designed for the integration requirements of modern data center and AI accelerator SoC designs, the IP implements the complete CXL 1.x protocol stack including CXL.io for PCIe-based I/O, CXL.cache for host cache coherency, and CXL.mem for device memory access, alongside ARB/MUX Link Management Packets, CXL Power Management VDM Packets, all CXL.cache/CXL.mem request and response messages, snoop responses, 32B and 64B cache line support, Protocol and Control flit type encoding, Multiple Data Header support, byte enable, link layer retry, and data poisoning. Its Address Translation Service support, configurable TC to VC queue mapping, Hot/Warm/Cold Reset support, QoS Telemetry, and Advanced Error Reporting give data center SoC teams a production-ready CXL 1.x controller.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations. Its parameterized architecture and clean host interface enable fast integration across a wide range of advanced process nodes.
