SmartDV’s CXL 2.0 Controller IP is a fully featured Compute Express Link solution purpose-built for SoC designs requiring CXL switching, memory pooling, and disaggregated memory connectivity in AI accelerator, HPC, and data center applications. Fully compliant with the CXL 2.0 specification and built on the PCIe 5.0 physical interface at 32 GT/s, it delivers the complete CXL 2.0 protocol stack including CXL.io, CXL.cache, and CXL.mem, alongside new CXL 2.0 capabilities for multi-level switching, memory pooling across multiple host processors, and device integrity and data encryption.
Designed for the advanced integration requirements of modern disaggregated memory and AI accelerator SoC designs, the IP implements all CXL 2.0 features including multi-host memory sharing and pooling, CXL switch support for connecting multiple CXL 1.x and 2.0 devices to a host processor, ARB/MUX Link Management Packets, all CXL.cache/CXL.mem request and response messages, complete snoop responses, 32B and 64B cache line support, Multiple Data Header, byte enable, link layer retry, data poisoning, Address Translation Service, QoS Telemetry, Advanced Error Reporting, and Hot/Warm/Cold Reset support.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations. Its parameterized architecture and clean host interface enable fast integration across a wide range of advanced process nodes.
