SmartDV’s UCIe 3.x Controller IP is a next-generation Universal Chiplet Interconnect Express solution engineered for the most demanding SoC and multi-die system designs requiring ultra-high-bandwidth, low-latency die-to-die connectivity across AI accelerators, high-performance computing, and next-generation data center chiplet architectures. Fully compliant with UCIe v3.0 and backward compatible with UCIe v2.0, v1.1, and v1.0, it delivers complete UCIe controller functionality supporting PCIe, CXL, and streaming protocols including AXI, CXS, and CHI at speeds up to 64 GT/s across 16, 32, and 64 lane configurations, providing a feature-complete die-to-die interconnect foundation for next-generation chiplet-based system designs.
As the semiconductor industry accelerates its transition to modular chiplet architectures, UCIe v3.0 doubles the maximum die-to-die bandwidth of v2.0 while adding runtime recalibration, priority sideband messaging, and low-power sideband operation. SmartDV’s UCIe 3.x Controller IP implements the complete UCIe v3.0 feature set spanning the Protocol Layer with AXI, CXL, CXS, PCIe, and CHI bridges, D2D Adapter Layer with Flit Pack, Flit Retry, CRC, and Parity, and APB Sideband with Protocol and Credit management, giving chiplet system teams a spec-complete, future-ready UCIe controller that addresses the most demanding AI and data center multi-die interconnect requirements.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized lane architecture, clock gating mechanism, and RDI TX/RX interface to the PHY enable fast integration and confident design bring-up across a wide range of advanced process nodes and chiplet packaging configurations.