SmartDV’s AMBA CHI Synthesizable Transactor is a fully featured AMBA 5 Coherent Hub Interface bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable CHI Requester and Completer node behavior during pre-silicon validation and software bring-up. Fully compliant with the latest ARM AMBA 5 CHI Architecture Specification, it delivers complete CHI master and slave functionality across the Protocol, Network, and Link layers, including all standard request node types (RN-F, RN-D, RN-I) and slave node types (SN-F, SN-I), giving validation teams a drop-in synthesizable CHI transactor ready for rapid integration into emulation and prototyping flows for fully coherent SoC and interconnect designs.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports link initialization with configurable skip and retry behavior, dynamic and pre-allocated credit control, cache model support in the master, all transaction types and opcodes, Direct Memory Transfer, Direct Cache Transfer, exclusive accesses, cache stashing, DVM operations, deallocating transactions, poison, and data check, enabling validation teams to exercise corner-case CHI behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its rich set of configuration parameters controlling CHI functionality, fine-grain control of requester, completer, and snooped node behavior, and on-the-fly port-level and system-level protocol and data checking enable rapid deployment for early software bring-up and system-level validation of fully coherent SoC designs.
