SmartDV’s AMBA AXI AIP is a fully featured SVA-based formal verification IP purpose-built for SoC designs requiring exhaustive, property-driven verification of AMBA AXI protocol compliance across high-performance interconnect, DMA, memory controller, and IP subsystem designs. Covering AXI3, AXI4, AXI4-Lite, AXI5, and AXI5-Lite interfaces, it delivers a comprehensive set of SystemVerilog Assertions targeting the full breadth of AXI protocol rules including channel handshake correctness, outstanding transaction ordering, write strobe validity, exclusive access atomicity, QoS signaling, and AXI5 atomic and cache stashing semantics.
Designed to complement simulation-based verification with the exhaustive state space exploration that only formal methods can provide, the AIP targets the class of subtle AXI protocol bugs including handshake deadlocks, out-of-order completion violations, exclusive access failures, and write data before address race conditions that are statistically unlikely to surface in directed or constrained-random simulation but can cause catastrophic data corruption in silicon. Its parameterized constraint and assumption architecture allows formal tools to focus verification effort on the most critical protocol properties while bounding the state space to tractable problem sizes.
Compatible with industry-standard formal verification tools and fully independent of any specific EDA vendor platform, the AIP integrates cleanly into existing formal flows with minimal setup overhead. Its modular property organization across read, write, and response channels, configurable protocol parameters, and clear assertion naming conventions enable verification teams to rapidly deploy, customize, and extend the property set to match the specific AXI configuration and design context of their SoC.
