SmartDV’s AMBA LTI Verification IP is a comprehensive solution for verifying the Local Translation Interface protocol, a point-to-point protocol that defines communication between I/O devices and Translation Buffer Units aligned with the Arm System MMUv3 architecture. Fully compliant with the AMBA LTI Protocol Specification Version E and backward compatible with earlier issues, it supports complete verification of LTI Master, Slave, Monitor, and Checker components across separate Request, Response, and Completion channels, covering all supported translation flows including Stall, ATST, NoStall, and PRI, with pipelining support and configurable signal widths.
SmartDV’s AMBA LTI VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With support for all LTI translation flows, pipelined Master and Slave interface operation, Realm Management Extension and Memory Encryption Context support, Device Permission Table verification, user signaling, error injection, on-the-fly protocol checking, built-in functional coverage, and a complete test suite, SmartDV’s AMBA LTI VIP enables verification teams to thoroughly validate local address translation subsystem designs for mobile, automotive, AI, and high-performance SoC applications.
