SmartDV’s Automotive SerDes PCS IP is a fully featured Physical Coding Sublayer solution purpose-built for automotive SoC designs requiring high-bandwidth, reliable serial connectivity for camera, display, and sensor applications across ADAS, autonomous driving, and in-vehicle infotainment systems. Fully compliant with the Automotive SerDes Alliance (ASA) Motion Link v2.1 specification and backward compatible with v2.0, v1.1, and v1.01, it delivers complete PHY and data link layer functionality supporting downlink data rates up to 16 Gbps and uplink data rates greater than 100 Mbps across multiple speed gears from 2 Gbps to 16 Gbps.
Designed to address the demanding signal integrity and functional safety requirements of modern automotive E/E architectures, the IP supports Application Stream Encapsulation and Decapsulation for video, I2C, Ethernet, SPI, GPIO, eDP, I2S, and test stream types, OAM for Operation Administration and Management, a comprehensive security framework with efficient key exchange and link layer security, time-division access mechanism, Precision Time Base, PAM2 and PAM4 gray encoding, RS-FEC encoding and decoding, PCS scrambling and descrambling, and clock recovery. Its FOFA forwarding fabric with normal and enumerate modes, half-duplex physical layer with asymmetric payload data rates, and light sleep power management give automotive SoC teams a production-ready ASA PCS implementation for next-generation automotive sensor and display connectivity.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations. Its parameterized speed gear architecture and clean host interface enable fast integration and confident design bring-up across a wide range of automotive process nodes.