Contact Us
Overview

SmartDV’s Automotive SerDes Alliance (ASA) Motion Link Verification IP is a comprehensive solution for verifying high-speed asymmetric serializer/deserializer designs for next-generation automotive camera, sensor, and display applications. Fully compliant with ASA Motion Link v2.1 and backward compatible with v2.0, v1.1, and v1.01, it supports complete verification of ASA PHY and data link layers, covering downstream data rates up to 16 Gbps and upstream data rates greater than 100 Mbps, all defined speed gears from 2 Gbps to 16 Gbps, PAM2 and PAM4 gray encoding, RS-FEC, and all defined startup phases across asymmetric half-duplex physical layer operation.

SmartDV’s ASA Motion Link VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.

With Application Stream Encapsulation and Decapsulation, comprehensive security framework verification, FOFA support, Motion Link Ethernet with symmetrical and asymmetrical types, Precision Time Base, light sleep, PCS scrambling, complete OAM coverage, and a full test suite, SmartDV’s ASA Motion Link VIP enables verification teams to thoroughly validate automotive SerDes designs for ADAS, autonomous driving, in-cabin displays, and high-bandwidth sensor connectivity applications.

Request Data Sheet
Automotive SerDes (ASA) VIP
Benefits
  • Full PHY and Data Link Layer Coverage – Supports complete ASA PHY and data link layer verification including PCS scrambling and descrambling, RS-FEC encoding and decoding, PAM2 mapping and PAM4 gray encoding, clock recovery, and half-duplex physical layer operation with asymmetric payload data rates separated by an Inter Burst Gap.
  • Comprehensive Speed Gear and Data Rate Support – Covers all ASA speed gears from 2 Gbps to 16 Gbps with downstream data rates up to 16 Gbps and upstream data rates greater than 100 Mbps, across all four startup phases including Startup Phase 1G, SGA, SGB, and SGC, with automatic startup into normal and test modes.
  • Application Stream Encapsulation and Decapsulation – Supports complete ASE and ASD operation for all ASEP stream types including video data, I2C, Ethernet frame, SPI, GPIO, embedded DisplayPort, I2S, CSI-2 ASEP, ASA Control Channel, and test ASEP streams, with time-division access mechanism and multiplexing and demultiplexing of application and internal data streams.
  • Security Framework and OAM Support – Covers the comprehensive ASA security framework including an efficient key exchange mechanism and link layer security, along with full OAM Operation, Administration, and Management verification for link monitoring and control.
  • FOFA and Motion Link Ethernet Support – Supports Forwarding Fabric normal and enumerate modes, and physical layer Motion Link Ethernet with both symmetrical and asymmetrical types across MII, GMII, and XGMII speed ranges, with 64b/65b and 4b/5b encoding for MLE.
  • Advanced PHY Feature Verification – Covers Precision Time Base for synchronization, light sleep duty cycling between active and disabled states, and all ASA v2.1 asymmetrical Ethernet capabilities introduced in the latest specification revision.
  • Complete Verification Infrastructure – Provides constraints randomization, status counters for bus events, and callbacks in transmitter and receiver for user-defined event handling and protocol and timing violation notification.
Compliance and Compatibility
  • Fully compliant with ASA Motion Link v2.1; backward compatible with v2.0, v1.1, and v1.01
  • Supports PAM2 and PAM4 physical layer signaling
  • Supports RS-FEC and PCS scrambling as per ASA specification
  • Compatible with UVM, OVM, VMM, SystemVerilog, and Verilog verification environments
  • Compatible with all major EDA simulators including Synopsys VCS, Cadence Xcelium, Siemens Questa, Aldec Riviera-PRO, and Verilator

Request Datasheet