SmartDV’s MIPI SPMI Slave IP is a silicon-proven, fully featured System Power Management Interface solution purpose-built for power management IC and peripheral SoC designs requiring reliable, low-latency communication with a SPMI master controller. Fully compliant with MIPI SPMI v2.0 and backward compatible with SPMI v1.0, it implements complete slave-side SPMI functionality with support for all command sequences, frame types, and power mode commands, making it an ideal solution for PMICs, regulators, and other power management peripherals in mobile and automotive SoC designs.
Designed to give peripheral and power management IC teams a production-tested, spec-complete SPMI slave implementation, the IP supports bus arbitration via Alert and SR bits, slave request hold functionality, Group Slave ID (GSID) support, and optional glitch suppression for enhanced signal integrity in noisy mobile environments. Its comprehensive power mode command support and robust frame handling make it a reliable, low-risk foundation for mobile and automotive power management peripheral designs.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration and confident design bring-up across a wide range of mobile and automotive process nodes and target applications.
