SmartDV’s AMBA AXI Synthesizable Transactor is a fully featured AMBA AXI bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable AXI master and slave behavior during pre-silicon validation and software bring-up. Fully compliant with the latest ARM AMBA AXI Protocol Specification, it covers AXI3, AXI4, AXI4-Lite, AXI5, and AXI5-Lite memory-mapped interfaces with complete master and slave functionality, separate address, data, and response phases, and separate read and write channels, giving validation teams a single, drop-in synthesizable AXI transactor that spans the full range of AXI memory-mapped protocol generations used in modern SoC designs.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports constrained randomization of protocol attributes, multiple outstanding transactions with out-of-order completion, narrow and unaligned transfer support, write strobe support, protected access modeling (Normal/Privileged, Secure/Non-secure, Data/Instruction), fine-grain per-address or per-transaction response control, programmable wait state and timeout insertion, and error injection during data transfer, enabling validation teams to exercise corner-case AXI behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its rich set of configuration parameters controlling AXI functionality, built-in testbench notification of significant events such as transactions, warnings, timing, and protocol violations, and status counters and callbacks for master and slave events enable rapid deployment for early software bring-up and system-level validation regardless of the underlying emulation platform.
