SmartDV’s MIPI SPMI Master IP is a silicon-proven, fully featured System Power Management Interface solution purpose-built for mobile, automotive, and high-performance embedded SoCs requiring reliable, low-latency power management communication between application processors and peripheral power management ICs. Fully compliant with MIPI SPMI v2.0, it implements complete master-side SPMI functionality with support for bus ownership transfer, authentication, device descriptor blocks, and advanced power mode management for the most demanding mobile and automotive power subsystem designs.
Designed to give SoC teams a production-tested, spec-complete SPMI master implementation, the IP supports the full command set including Command, Data/Address, and No Response frames, Connect/Disconnect sequences, extended register read/write, and ACK/NACK response handling. Its master priority arbitration, baud rate control, and low power mode support make it a comprehensive and flexible power management bus controller well-suited for complex multi-device PMIC topologies in mobile and automotive applications.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration and confident design bring-up across a wide range of mobile and automotive process nodes and target applications.
