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MIPI SPMI Slave to AHB Bridge IP

Design IP
Overview

SmartDV’s MIPI SPMI Slave to AHB Bridge IP is a silicon-proven, fully featured power management interface bridge solution purpose-built for SoC designs requiring seamless connectivity between an external SPMI master controller and an AMBA AHB-based on-chip interconnect. Fully compliant with MIPI SPMI v2.0 and AMBA AHB5, it enables direct read and write access to AHB-mapped registers and peripherals from a standard SPMI master interface, significantly simplifying power management integration and register access workflows for AHB-based SoC designs.

By bridging the SPMI slave interface directly to the AHB bus fabric, it provides a lightweight, standards-compliant path for power management controllers to access the full AHB address space without requiring dedicated register infrastructure. Its support for Authentication Command Sequences, Device Descriptor Blocks, slave request hold, and optional glitch suppression gives SoC and PMIC teams a production-tested, feature-rich bridge implementation that goes well beyond basic SPMI-to-AHB connectivity.

Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean bridge interface enable fast integration and confident design bring-up across a wide range of mobile and automotive process nodes and target applications.

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MIPI SPMI Slave to AHB Bridge
Benefits
  • Full MIPI SPMI Slave to AHB Bridge Functionality – Complete SPMI slave implementation with direct read/write access to AHB-mapped registers and peripherals via SPMI master interface
  • Full SPMI Frame Support – Command, Data/Address, and No Response frame handling per MIPI SPMI v2.0 specification
  • Advanced Authentication and Device Management – Authentication Command Sequence and Device Descriptor Block Command Sequence support for secure, standards-compliant device initialization
  • Slave Request and Hold Support – Alert bit and SR bit slave request support with slave request hold functionality for reliable bus access management
  • Robust Communication – ACK/NACK response handling, extended register read/write, and wakeup command support for reliable SPMI bus operation
  • Optional Glitch Suppression – Configurable glitch suppression on the SPMI bus for enhanced signal integrity in noisy mobile environments
  • Full AHB Protocol Support – All transfer types, burst transfers, and response types supported per AMBA AHB5 specification
Compliance and Compatibility
  • Fully compliant with MIPI SPMI v2.0 specification
  • Fully compliant with ARM AMBA AHB5 specification
  • Configurable SoC interface supporting custom wrappers for seamless integration
  • Compatible with ASIC and FPGA design flows across leading foundry process nodes
  • Compatible with all major EDA synthesis, simulation, and linting flows

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