SmartDV’s MIPI ASPMI Slave IP is a silicon-proven, fully featured System Power Management Interface solution purpose-built for mobile, automotive, and high-performance embedded SoCs requiring reliable, low-latency power management communication between application processors and peripheral power management ICs. Fully compliant with MIPI SPMI v2.0 and ASPMI v2.3, it implements complete slave-side SPMI functionality with an extensive feature set covering authentication, device descriptor blocks, virtual wires, and advanced interrupt management.
What distinguishes this IP is the depth of its interrupt and power management architecture. With support for edge and level sensitive interrupts, group interrupts, SPS interrupts, DVC group interrupts, LDO and DVC interrupts, interrupt priority queuing, and IRQH enable control, it gives SoC teams a production-tested, feature-rich ASPMI slave implementation that goes well beyond basic protocol compliance. Its support for Slave-to-Slave command filtering, SGPIO functionality, and Authentication Command Sequences further positions it as a comprehensive solution for advanced mobile and automotive power management designs.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration and confident design bring-up across a wide range of mobile and automotive process nodes and target applications.
