SmartDV’s MIPI SPMI Verification IP is a comprehensive solution for verifying the MIPI System Power Management Interface, the two-wire serial bus standard connecting the integrated power controller of an SoC processor with one or more power management IC voltage regulation systems in mobile and portable devices. Fully compliant with MIPI SPMI v2.0 and backward compatible with v1.0, it supports complete verification of SPMI master and slave components across all defined topologies with up to 4 masters and up to 16 slaves per bus, all SPMI command types, all power mode commands, all frame types, all master bus connection mechanisms, group slave ID, device enumeration, and ACK/NACK generation as defined in SPMI v2.0.
SmartDV’s MIPI SPMI VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With comprehensive glitch injection and detection on both SDATA and SCLK, slave request handling via Alert bit and Slave Request Bit, master and slave arbitration, half-speed and full-speed mode support, bus-accurate timing, built-in functional coverage, and a complete test suite, SmartDV’s MIPI SPMI VIP enables verification teams to thoroughly validate SPMI power management interface designs for smartphones, tablets, wearables, and IoT devices requiring dynamic voltage scaling and real-time power control.
