SmartDV’s MIPI I3C SMaster IP is a silicon-proven, fully featured I3C controller solution purpose-built for SoC designs requiring the complete range of I3C bus roles — Master, Secondary Master, and Slave — in a single, unified IP core. Fully compliant with MIPI I3C v1.2 and optionally with MIPI I3C HCI v1.2, it delivers the most comprehensive I3C implementation in SmartDV’s portfolio, supporting all bus topologies, the full HDR mode suite, dynamic multi-master operation, and seamless legacy I2C device co-existence over a minimal-pin two-wire interface.
Designed for complex multi-master SoC architectures where a single component must dynamically assume different bus roles, the IP supports Secondary Master interrupt handling, full master handoff, and complete slave functionality alongside its primary master capabilities. Its support for JEDEC Module Sideband Bus v1.0 and MCTP I3C Transport Binding v3.0 — including MCTP counters for IBI in slave mode — further extends its applicability to server, memory module, and data center management use cases beyond its core mobile and IoT applications.
Built for design flexibility and silicon efficiency, the IP core is available in both HCI and non-HCI variants to accommodate gate-count-sensitive designs, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture, dual PIO and DMA operating modes, and optional HCI interface for OS-level driver compatibility enable fast integration and confident design bring-up across a wide range of process nodes and target applications.
