SmartDV’s MIPI I3C Synthesizable Transactor is a fully featured MIPI I3C bus model purpose-built for hardware emulation and FPGA prototyping environments requiring fast, accurate, and highly configurable I3C Controller and Target behavior during pre-silicon validation and software bring-up. Fully compliant with MIPI I3C v1.2, it delivers complete Controller and Target functionality across all I3C device types and all standard bus topologies, with legacy I2C device co-existence, giving validation teams a drop-in synthesizable I3C transactor ready for rapid integration into emulation and prototyping flows for mobile, IoT, and automotive peripheral validation.
Designed for the speed and visibility demands of emulation and FPGA prototyping rather than ASIC tape-out, the transactor emphasizes fast bring-up, fine-grained controllability, and on-the-fly protocol checking over area or power optimization. It supports Dynamic Address Assignment, Static Addressing for legacy I2C devices, I3C address arbitration, SDR and HDR-DDR messaging, all Common Command Codes, In-Band Interrupt, Hot-Join, and mixed message type support, enabling validation teams to exercise corner-case I3C behavior that is difficult to reach with production RTL alone.
Built for fast compile times and efficient resource utilization on hardware emulation and FPGA prototyping platforms, the transactor is fully synthesizable and platform-independent, deploying without modification across any major emulation or prototyping environment. Its comprehensive Controller and Target error injection suite covering S0-S5 and M0-M1 error categories and HDR error types, combined with rich configuration parameters controlling I3C functionality, enable rapid deployment for early software bring-up and system-level validation regardless of the underlying emulation platform.
