SmartDV’s MIPI Debug over I3C Target IP is a silicon-proven, fully featured debug and trace interface solution purpose-built for SoC designs requiring minimal-pin, standards-compliant debug access across mobile, IoT, automotive, and high-performance embedded systems. Fully compliant with MIPI Debug Over I3C v1.1, it implements complete target-side debug functionality over the MIPI I3C interface, enabling efficient transport of debug controls and data between a debug and test system and the target system across a shared, low-bandwidth I3C bus.
Designed for the complex debug requirements of modern multi-component SoC systems, the IP integrates a full I3C slave implementation with CCC, Hot Join, IBI, DAA, and HDR mode support alongside complete Link and Network/Transport layer functionality. Its support for up to 16 network adaptors spanning SPP, STP, SAM, TWP, and UART protocols gives SoC teams a scalable, flexible debug infrastructure that accommodates diverse debug and trace transport requirements within a single, unified interface solution.
Built for design flexibility and silicon efficiency, the IP core is highly configurable for both ASIC and FPGA implementations, with a strong focus on area optimization, power management, and peak performance. Its parameterized architecture and clean host interface enable fast integration and confident design bring-up across a wide range of process nodes and target applications.
