SmartDV’s MIPI Debug Over I3C Verification IP is a comprehensive solution for verifying the MIPI Debug Over I3C interface, a bare-metal, minimal-pin debug and trace interface for transporting debug controls and data between a Debug and Test System and a Target System over the MIPI I3C bus. Fully compliant with MIPI Debug Over I3C v1.1 (May 2024) and based on MIPI I3C v1.1.1, it supports complete verification of DTS controller and TS device components across dedicated debug and shared bus topologies, covering full I3C slave operation with Hot Join, IBI, DAA, and HDR modes, complete link and network/transport layer functionality, up to 16 network adaptors, all Debug Common Command Codes, Debug Network Adaptor Operation Commands, and Debug In-Band Interrupts.
SmartDV’s MIPI Debug Over I3C VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With support for SPP, STP, SAM, TWP, and UART network adaptors, group addressing for multicast debug transfers, timing control with message timestamps, all defined DBGOPCODE and DBGACTION commands, comprehensive IBI cause coverage, built-in functional coverage, and a complete test suite, SmartDV’s MIPI Debug Over I3C VIP enables verification teams to thoroughly validate debug interface designs for mobile SoCs, IoT devices, automotive ECUs, and any power-managed multi-component system requiring scalable dynamic debug connectivity.
