SmartDV’s JTAG Verification IP is a comprehensive solution for verifying the Joint Test Action Group boundary-scan interface, the industry-standard Test Access Port architecture for testing interconnections, debugging integrated circuits, and observing or modifying circuit activity during normal operation. Fully compliant with IEEE 1149.1-2013 (Standard Test Access Port and Boundary-Scan Architecture) and IEEE 1149.6-2003 (Boundary-Scan of Advanced Digital Networks), it supports complete verification of JTAG TAP controller and TAP instruction and data generator components, all defined TAP instructions, instruction and data registers up to 64 bits, user-defined instruction and register extensibility, and automatic BSDL-driven test vector, functional coverage, and SVA assertion generation.
SmartDV’s JTAG VIP supports UVM, SystemVerilog, and Verilog, and integrates seamlessly into diverse verification environments. It is simulator-independent and compatible with all leading EDA simulators, providing flexibility across simulation platforms.
With configurable clock frequency, comprehensive state-based and command protocol checking, user-defined TAP state callbacks, custom instruction decoder support, functional safety features aligned with safety-critical development processes, built-in functional coverage, and a complete test suite, SmartDV’s JTAG VIP enables verification teams to thoroughly validate JTAG test and debug interfaces for SoCs, FPGAs, automotive, aerospace, and safety-critical embedded systems.
