SmartDV’s JTAG AIP is a fully featured SVA-based formal verification IP purpose-built for SoC designs requiring exhaustive, property-driven verification of JTAG boundary scan protocol compliance across debug infrastructure, test access port, and boundary scan chain designs. Fully compliant with IEEE 1149.1-2013 and IEEE 1149.6, it delivers a comprehensive set of SystemVerilog Assertions targeting the full breadth of JTAG protocol rules including TAP controller state machine correctness, instruction register sequencing, data register capture and update timing, boundary scan cell behavior, and IEEE 1149.6 AC-coupled signal properties.
Designed to complement simulation-based verification with the exhaustive state space exploration that only formal methods can provide, the AIP targets the class of subtle JTAG protocol bugs including illegal TAP state transitions, instruction register violations, boundary scan cell sequencing errors, and AC-coupled signal timing failures that are statistically unlikely to surface in directed or constrained-random simulation but can render debug infrastructure non-functional in silicon. Its parameterized constraint and assumption architecture allows formal tools to focus verification effort on the most critical protocol properties while bounding the state space to tractable problem sizes.
Compatible with industry-standard formal verification tools and fully independent of any specific EDA vendor platform, the AIP integrates cleanly into existing formal flows with minimal setup overhead. Its modular property organization, configurable instruction and data register parameters, and clear assertion naming conventions enable verification teams to rapidly deploy, customize, and extend the property set to match the specific JTAG configuration and design context of their SoC.
